[tracing] Add uniform tracing support for VCS and Verilator.

Created by: zchamski

Purpose

This PR adds a uniform support for waveform collection using Verilator and VCS.

Overview

The PR introduces a scheme for controlling waveform generation both at the elaboration and the execution of simulation models in VCS- and Verilator-based environments. The process of waveform generation is controlled by two environment variables:

• TRACE_COMPACT (default: empty): When non-empty, activates generation and collection of the most compact waveform format available on the given platform, usually at the expense of compilation and simulation speed.
• TRACE_FAST (default: empty): When non-empty, activates generation and collection of the fastest waveform format available on the chosen simulation platform (as selected by setting variable DV_SIMULATORS).

Because of limitations of Verilator, TRACE_COMPACT and TRACE_FAST are mutually exclusive and require separate builds of verilated models. This mutual exclusion is enforced by explicit tests in cva6/sim/Makefile.

The waveform trace files generated during simulation are copied to per-test output directory cva6/sim/out_<date>/<sim_platform>_sim/ and have the name of the currect target appended to the stm of the test name. This ensures that waveform files from simulations on distinct target platforms within a single simulation run are not overwritten by successive invocations.

Waveform files

Four distinct waveform formats can be generated, depending on the simulator used:

• using Verilator:

  • when TRACE_COMPACT is set and non-empty, the simulation will produce an FST trace. FST is the most compact format available, but requires a substantial amount of compilation time when processing Verilator output. FST traces can be read directly by GTKwave and can be converted to VCD then to a proprietary format of any CAD tool.
  • when TRACE_FAST is set and non-empty, the simulation will produce a VCD trace file. VCD is the most verbose and space-hungry format available, but it offers shorter turnaround times for compilation and simulation of a design. It also universally supported.

• using Synopsys VCS:

  • when TRACE_COMPACT is set and non-empty, the simulation will produce an FSDB trace. FSDB is a proprietary format of Synopsys, more compact that the alternative VPD (VCDplus) format. FSDB traces can be read directly by Synopsys tools, or can be converted VCD then to the FST format of supported eby GTKwave.

• when TRACE_FASTis set and non-empty, the simulation will produce aVPD` trace file. VPD is a compressed eformat derived from VCS and results in slightly larger files that when using the FSDB format, but it offers shorter turnaround times for compilation and simulation of a design and does not depend on the availability of additional Synopsys tools such as Verdi.

Benchmarking (very preliminary)

Waveform file size (cva6/regress/issue-tests.sh, CV64A6, 3694 cycles)

Format	Raw size (bytes)	Size increase
FST	769883	-
FSDB	1456200	+0.89x
VPD	1753649	+1.27x
VCD	52873264	+67.7x

Changelog

• cva6/sim/Makefile (DEBUG): Default to empty. Add lead comment. (TRACE_FAST): Default to empty. (TRACE_COMPACT): Ditto. (TRACE_FAST, TRACE_COMPACT): Enforce mutual exclusion and dependence on DEBUG. (DEBUG, TRACE_FAST, TRACE_COMPACT): Export to environment. (veri-testharness): Request appropriate trace mode and a matching trace file name. Copy trace file to per-test directory, adding target name suffix to avoid cross-target overwriting of waveform files. (ALL_UVM_FLAGS): Add options according to interactive/batch config. (SIMV_TRACE_EXT): Select trace extension according to requested trace mode. (vcs_uvm_run): Copy waveform files (if present) to verification log dir. (vcs-uvm): Copy waveform files (if present) from verification log dir to per-test directory, adding target-specific suffix. (vcs_clean_all): Also remove FSDB waveform files. (clean_all): Remove all supported types of waveform files.
• cva6/sim/cva6.py (run_assembly): Increase timeout on ISS simulation runs to 1200s (20 min).
• cva6/sim/init_run_uvm.do: New VCS script.
• cva6/sim/init_run_uvm_vpd.do: Ditto.

Signed-off-by: Zbigniew Chamski zbigniew.chamski@thalesgroup.com