Add dm_exception_addr_i port to riscv_core.
Created by: silabs-PaulZ
This PR will add the dm_exception_addr_i to the top-level riscv_core. This PR must be done in conjunction with the design update that adds this pin: https://github.com/openhwgroup/cv32e40p/pull/353
This PR will fixe the following issues: https://github.com/openhwgroup/cv32e40p/issues/185 https://github.com/openhwgroup/core-v-docs/issues/62
Signed-off-by: Paul Zavalney paul.zavalney@silabs.com