Fix sources so the Verible git hook will pass.

Created by: jeremybennett

For some reason a whole load of changes were committed which do
not pass the pre-commit hook.

Files changed:

* rtl/core-v-mcu/components/apb_soc_ctrl.sv: Update formatting
with Verible.
* rtl/core-v-mcu/efpga_subsystem/A2_fifo_ctl.sv: Likewise.
* rtl/core-v-mcu/fc/cv32e40p_fp_wrapper.sv: Likewise.
* rtl/core-v-mcu/soc/soc_event_arbiter.sv: Likewise.
* rtl/core-v-mcu/soc/soc_event_generator.sv: Likewise.
* rtl/core-v-mcu/soc/soc_interconnect.sv: Likewise.
* rtl/core-v-mcu/soc/soc_interconnect_wrap.sv: Likewise.
* rtl/core-v-mcu/soc/soc_peripherals.sv: Likewise.
* rtl/core-v-mcu/top/pad_frame.sv: Likewise.
* rtl/core-v-mcu/top/soc_domain.sv: Likewise.
* rtl/efpga/data/top.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/SPI_slave.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbaps.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbclp.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbfsr.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbmic.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbpif.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbrfu.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbrwf.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbsmc.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/fcbssc.sv: Likewise.
* rtl/efpga/ql_fcb/rtl/ql_generic_gates.sv: Likewise.
* rtl/efpga/top.sv: Likewise.

Signed-off-by: Jeremy Bennett jeremy.bennett@embecosm.com