Generate the Verilator model as a library

Created by: jeremybennett

This modifies the cores, to give a `model-lib` target which will
create a Verilator model as a library.  This can then be used by
other projects, which will link in the Verilator model as a
library.

The first projects which will use this are a debug server to drive
the Verilator model and a tool to execute binaries to completion.

Files changed:

* README.md: Describe generating the Verilator library.
* rtl/core-v-mcu/core-v-mcu.core: Add model-lib target, which in
turn needs a pre-build hook and associated script.
* rtl/core-v-mcu/scripts/vedit.sh: Created.
* rtl/vendor/openhwgroup_cv32e40p.core: Add files_sim fileset to
the default target for the model-lib target.
* rtl/vendor/openhwgroup_cv32e40p_tracing.core: Likewise.
* rtl/vendor/pulp_plaform_tech_cells_generic.core: Likewise.

Signed-off-by: Jeremy Bennett jeremy.bennett@embecosm.com