- Jul 20, 2022
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davide schiavone authored
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- Jul 18, 2022
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davide schiavone authored
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davide schiavone authored
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davide schiavone authored
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- Jun 22, 2022
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Florian Zaruba authored
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- Jun 17, 2022
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Massimiliano Giacometti authored
Co-authored-by: Massimiliano Giacometti <max@openhwgroup.org>
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- Jun 06, 2022
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davide schiavone authored
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- Jun 01, 2022
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davide schiavone authored
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Davide Schiavone authored
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davide schiavone authored
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- May 26, 2022
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Davide Schiavone authored
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Schiavone Pasquale Davide authored
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Davide Schiavone authored
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Davide Schiavone authored
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- May 20, 2022
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Schiavone Pasquale Davide authored
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Davide Schiavone authored
* update CORE-V-MCU Quick Start Guide for WLS2 users * updates for apt dependencies
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- May 17, 2022
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davide schiavone authored
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- Apr 12, 2022
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Mike Thompson authored
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Mike Thompson authored
Nexys A7 - Ashling Opella-LD connection details added
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promodkumar-ashling authored
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promodkumar-ashling authored
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Promodkumar CM authored
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Promodkumar CM authored
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- Mar 29, 2022
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Mike Thompson authored
* Initial steps towards regressionable tests Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Respond to gmartin feedback: Pseudo UART enabled by default Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Add XSIM compile-time guard Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Clarify JTAG port operation Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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Mike Thompson authored
* Initial steps towards regressionable tests Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Initial steps towards regressionable tests Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Respond to gmartin feedback: Pseudo UART enabled by default Signed-off-by: Mike Thompson <mike@openhwgroup.org> * Add XSIM compile-time guard Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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- Mar 28, 2022
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Massimiliano Giacometti authored
Signed-off-by: Massimiliano Giacometti <max@openhwgroup.org> Co-authored-by: Massimiliano Giacometti <max@openhwgroup.org>
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- Mar 23, 2022
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Mike Thompson authored
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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- Mar 19, 2022
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Mike Thompson authored
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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- Mar 18, 2022
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Mike Thompson authored
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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Mike Thompson authored
Signed-off-by: Mike Thompson <mike@openhwgroup.org>
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- Mar 15, 2022
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Mike Thompson authored
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Mike Thompson authored
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Mike Thompson authored
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- Mar 12, 2022
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Greg Martin authored
* Dev 1 (#208) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Removal of Floating point unit Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed FLL address decode problem Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <gmartin@quicklogic.com> * removed vendor specific model Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <gmartin@quicklogic.com> * removed stale file Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * More Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * More Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Vendor `axi` Co-authored-by: Someshwar M S <someshwar.ms@optimuslogic.in> Co-authored-by: Florian Zaruba <florian@openhwgroup.org> * Updated `dev` branch (#209) * updated for no_cluster fixes gf22 iopads Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Xcelium changes for fusesoc Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Xcelium simulation with Perceptia model generates 3 different clocks now. * Increase address size for PLL registers Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Re-adjustement of pll address space from incorrect 4 bits to 3 bits Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Made changes in bootloader to accommodate the 3 bit register changes. Now the application code also comes up. * In perceptia model has some issue with divison. Made a change to keep our changes minimal and keep it as close as to the original code. The check of pll_period within a range is now enabled. Works fine. Bootloader and app also comes up. * Made changes in clk_and_control.sv to match the have more registers in FLL as the address bits are now increased to 3 bits. Made changes in bootloader and application software as well to reflect these changes. Able to boot into the CLI test application. * Reverted changes done in Perceptia model as the divide issue was because of un initialized registers in clk_and_ctrl.sv. * Added a function to set the PLL frequency which can be called multiple times to set SOC, peripheral and cluster clocks. * Added the r_tmp variable usage back in clk_and_control.sv. * Booloader now does not configure the PLL, instead puts into bypass and runs at reference clock. The application configures the PLL to 400 MHz, 200 MHz and 100 MHz. The bootloader and application is booting. In the tests, it looks like advance timer tests are getting stuck. * incomplete cleanup of bootrom Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Additional synthesis cleanup. ref clock adjustment for emulation Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Removal of Floating point unit Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed FLL address decode problem Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Cleanup of A2 bootloader code. 0 Errors and 0 Warnings. Added some comments as well. * Adding latest cli test app mem files. * formatted various files Signed-off-by: Greg Martin <gmartin@quicklogic.com> * removed vendor specific model Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Watchdog timer debug related changes. * Watchdog fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Updated cli_test memory files for simulation Signed-off-by: Greg Martin <gmartin@quicklogic.com> * removed stale file Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * More Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * More Lint fixes Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed makefile to re-run format after emulation build Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixed some blocking/nonblocking assignements Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Vendor `axi` Co-authored-by: Greg Martin <gmartin@quicklogic.com> Co-authored-by: Someshwar M S <someshwar.ms@optimuslogic.in> * Added support for building emulation on Genesys2 FPGA board Signed-off-by: Greg Martin <gmartin@quicklogic.com> * fixed docs/Makefile for Nexys -- still needs genesys doc support Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Bootloader changes for UART srec boot Signed-off-by: Greg Martin <gmartin@quicklogic.com> * FIx Makefile to run format after ioscript Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Addedd missing include files for bootloader Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Delete spi.h Unused file * Delete PerceptiaPLL_reg_defs.h Unused file * Fixes to Verilator clock generation and re-inclusion of verilatorBoot.mem file Signed-off-by: Greg Martin <gmartin@quicklogic.com> * Fixes to Verilator clock generation Signed-off-by: Greg Martin <gmartin@quicklogic.com> Co-authored-by: Someshwar M S <someshwar.ms@optimuslogic.in> Co-authored-by: Florian Zaruba <florian@openhwgroup.org>
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- Mar 08, 2022
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suppamax authored
Signed-off-by: Massimiliano Giacometti <max@openhwgroup.org> Co-authored-by: Massimiliano Giacometti <max@openhwgroup.org>
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- Mar 02, 2022
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Mike Thompson authored
qsg readme updates
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Mike Thompson authored
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- Mar 01, 2022
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Mike Thompson authored
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Mike Thompson authored
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- Feb 28, 2022
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rickoco authored
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