Purpose of AXI_BUS, axi_master_connect dependency with axi_switch_vif in uvm_testbench
Created by: dvusingh
Hi,
I observed that in the cva6_tb_wrapper.sv file,
- we are connecting axi_interface signal based on axi_switch_vif as done in below assign statement **assign axi_ariane_resp.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;
Now again we are doing the same assignment, as axi_switch_vif.active =1 assign axi_slave.aw_ready = (axi_switch_vif.active) ? axi_slave.aw_ready : cva6_axi_bus.aw_ready;**
we have AXI_BUS instance and axi_master_connect instance
AXI_BUS.Master master ); assign master.aw_id = dis_mem? '0 : axi_req_i.aw.id; assign master.aw_addr = dis_mem? '0 : axi_req_i.aw.addr;
Here, master.aw_addr=0.
- later we are connecting the axi2mem with sram for instruction and data storage
What is the purpose of connecting AXI_BUS and axi_master_connect with cva6 using axi_switch_vif?
I am not able to understand this can anyone explain.
Thanks