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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Yocto layer for CVA6

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Unofficial development fork of U-Boot

CV32E40X Design-Verification environment

4 stage, in-order, secure RISC-V core based on the CV32E40P

RTL code for implementation of dual-core trusted MCU

CV32E40S Design-Verification environment

Run an AWS CodeBuild project as a step in a GitHub Actions workflow job.

CORE-V MCU DevKit drivers written with AWS CommonIO approach

Main Repo for the OpenHW Group Software Task Group

Advanced Verification Methodologies for RISC-V and related IP

Unified Access Page for the TRISTAN project