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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

CORE-V MCU UVM Environment and Test Bench

Small and simple APB interrupt controller

CV32E40S Design-Verification environment

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

Advanced Verification Methodologies for RISC-V and related IP

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

CV32E40X Design-Verification environment

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

The purpose of the repo is to support CORE-V Wally architectural verification

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Functional verification project for the CORE-V family of RISC-V cores.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.