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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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Instruction Set Generator initially contributed by Futurewei
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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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Functional verification project for the CORE-V family of RISC-V cores.
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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
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The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
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Instruction Set Generator initially contributed by Futurewei
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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Updated -
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
Updated