Explore projects
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Michael Zigldrum / DNS Zone Manager
Apache License 2.0Updated -
OpenHW Group / backup-20231210 / apb_interrupt_cntrl
Apache License 2.0Small and simple APB interrupt controller
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OpenHW Group / backup-20231210 / corev-qemu
GNU Lesser General Public License v2.1 onlyOfficial QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
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OpenHW Group / backup-20231210 / cva5
Apache License 2.0The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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Functional verification project for the CORE-V family of RISC-V cores.
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OpenHW Group / backup-20231210 / cve2
Apache License 2.0The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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OpenHW Group / backup-20231210 / cv32e40s-dv
Apache License 2.0CV32E40S Design-Verification environment
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This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
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OpenHW Group / backup-20231210 / cv32e40s
Apache License 2.04 stage, in-order, secure RISC-V core based on the CV32E40P
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OpenHW Group / backup-20231210 / core-v-freertos
Apache License 2.0Updated -
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
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