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Small and simple APB interrupt controller

Linux kernel source tree

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Functional verification project for the CORE-V family of RISC-V cores.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

CV32E40S Design-Verification environment

The OpenPiton Platform

This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.

Unofficial development fork of U-Boot

4 stage, in-order, secure RISC-V core based on the CV32E40P

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.