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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Unofficial development fork of U-Boot

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Eclipse/FreeRTOS/core-v-mcu example program

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

4 stage, in-order, secure RISC-V core based on the CV32E40P

4 stage, in-order, compute RISC-V core based on the CV32E40P

Small and simple APB interrupt controller

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.