Explore projects

4 stage, in-order, compute RISC-V core based on the CV32E40P

4 stage, in-order, compute RISC-V core based on the CV32E40P

CV32E40X Design-Verification environment

CV32E40X Design-Verification environment

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.