Explore projects

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Functional verification project for the CORE-V family of RISC-V cores.

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.