Explore projects
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OpenHW Group / backup-20240421 / force-riscv
Apache License 2.0Instruction Set Generator initially contributed by Futurewei
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OpenHW Group / backup-20240421 / cve2
Apache License 2.0The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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Documentation for the OpenHW Group's set of CORE-V RISC-V cores
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OpenHW Group / backup-20240421 / corev-binutils-gdb
GNU Library General Public License v2 onlyUpdated -
OpenHW Group / backup-20240421 / cva5
Apache License 2.0The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
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OpenHW Group / backup-20240421 / cv32e40s-dv
Apache License 2.0CV32E40S Design-Verification environment
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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
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CV32E40X Design-Verification environment
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OpenHW Group / backup-20240421 / core-v-freertos
Apache License 2.0Updated -
Functional verification project for the CORE-V family of RISC-V cores.
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OpenHW Group / backup-20240421 / cv32e41p
Apache License 2.04 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
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Martin Lowe / git-eca-rest-api
Eclipse Public License 2.0Updated -
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Leonardo Militano / VO-WoT
MIT LicenseUpdated -
Martin Lowe / eclipsefdn-uss-api
Apache License 2.0Updated -
Martin Lowe / eclipsefdn-profile-api
Apache License 2.0Updated