Explore projects

A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.

CV32E40S Design-Verification environment

CV32E40X Design-Verification environment

Yocto layer for CVA6

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Unofficial development fork of U-Boot

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Instruction Set Generator initially contributed by Futurewei

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Functional verification project for the CORE-V family of RISC-V cores.

Aidge export to ASYGN Colibry NPU