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Instruction Set Generator initially contributed by Futurewei

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Functional verification project for the CORE-V family of RISC-V cores.

A website that enables Foundation staff to blog on our domain.

PPE - Privacy Protection Enforcement

Aidge export to OpenVX, tailored for TIOVX (targeting DRA829 processors)

Aidge export to pure C source code, with properties favoring the certification of the code

Aidge's ACETONE-based CPU backend, written in C, not optimized for performances

Eclipse Foundation Solstice Theme for Hugo!

A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.

CV32E40S Design-Verification environment

CV32E40X Design-Verification environment