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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Yocto layer for CVA6

The OpenPiton Platform

CORE-V Family of RISC-V Cores

Linux kernel source tree

CORE-V MCU UVM Environment and Test Bench

Instruction Set Generator initially contributed by Futurewei

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

Eclipse/FreeRTOS/core-v-mcu example program

CORE-V MCU DevKit drivers written with AWS CommonIO approach