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Repository for AWS Infrastructure (Docker, Documentation, etc.)
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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downloads.openhwgroup.org
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Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board
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Unofficial development fork of U-Boot
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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
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Small and simple APB interrupt controller
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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.
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Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
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4 stage, in-order, secure RISC-V core based on the CV32E40P
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Eclipse/FreeRTOS/core-v-mcu example program
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Linux kernel source tree
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Instruction Set Generator initially contributed by Futurewei