Explore projects

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

4 stage, in-order, secure RISC-V core based on the CV32E40P

4 stage, in-order, compute RISC-V core based on the CV32E40P

Small and simple APB interrupt controller

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Instruction Set Generator initially contributed by Futurewei

Main Repo for the OpenHW Group Software Task Group

CORE-V Family of RISC-V Cores

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores