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This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Instruction Set Generator initially contributed by Futurewei

Main Repo for the OpenHW Group Software Task Group

CORE-V Family of RISC-V Cores

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

CVA6 SDK containing RISC-V tools and Buildroot

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Website documentation for the Eclipse Foundation chat service

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.