Explore projects

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

This Aidge module compresses CNNs through tensor decomposition

This repository contains the sources for the Eclipse Project Handbook. All content is represented in Asciidoc format and Asciidoctor is used to render the content into HTML, PDF, and EPUB formats. Note that the documents are all rendered complete (i.e. images and other resources are embedded).

StatET (Main Repo)

A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.

UVM Verification Environment for the CVFPU

The purpose of the repo is to support CORE-V Wally architectural verification

Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.

RTL code for implementation of dual-core trusted MCU

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

Example SDK applications for DevKit

CORE-V MCU DevKit drivers written with AWS CommonIO approach

CV32E40S Design-Verification environment

Unified RISC-V Access Platform project repository

CV32E40X Design-Verification environment

Yocto layer for CVA6