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Unified RISC-V Access Platform project repository

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Functional verification project for the CORE-V family of RISC-V cores.

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

The Eclipse Sparkplug Working Group seeks to drive the evolution and broad adoption of the Eclipse Sparkplug protocol and related technologies that enable the creation of open, collaborative, and interoperable Industrial IoT (IIoT) solutions.

Implementation of Matrix Web client: elementweb hosted at Eclipse and accessible at https://chat.eclipse.org

This is the repository corresponding to Oniro WG and TLP landing page, made public on 2021-10-26