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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Functional verification project for the CORE-V family of RISC-V cores.

This project maintains the official Technology Compatiblity Kit (TCK) for the AsciiDoc language and its APIs.

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass

Aidge export to ASYGN Colibry NPU

The Eclipse Sparkplug Working Group seeks to drive the evolution and broad adoption of the Eclipse Sparkplug protocol and related technologies that enable the creation of open, collaborative, and interoperable Industrial IoT (IIoT) solutions.

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

Tools for Software Composition Analysis