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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
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OpenHW Group / backup-20240512 / cvfpu
Apache License 2.0Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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OpenHW Group / backup-20240512 / cve2
Apache License 2.0The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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OpenHW Group / backup-20240512 / cva6
Apache License 2.0The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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OpenHW Group / backup-20240512 / cv32e40p
Apache License 2.0CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
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Functional verification project for the CORE-V family of RISC-V cores.
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