Functional verification project for the CORE-V family of RISC-V cores.
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
CV32E40X Design-Verification environment
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.