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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
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OpenHW Group / backup-20240512 / cve2
Apache License 2.0The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
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OpenHW Group / backup-20240512 / cvfpu
Apache License 2.0Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
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Eclipse/FreeRTOS/core-v-mcu example program
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RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
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Unified Access Page for the TRISTAN project
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Eclipse Projects / Eclipse Plato / www
Creative Commons Attribution 4.0 InternationalUpdated -
Eclipse Projects / Eclipse openpass / gt-gen-core
Eclipse Public License 2.0GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.
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Eclipse Foundation / IT / Websites / automotive-oss.org
Eclipse Public License 2.0Updated -
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Eclipse Projects / Eclipse openpass / openscenario1-engine
Eclipse Public License 2.0Updated -
Eclipse Foundation / IT / Websites / marketplace.eclipse.org
Eclipse Public License 2.0Updated -
Eclipse Projects / aidge / aidge_export_cpp
Eclipse Public License 2.0Aidge's reference C++ export module, required for generating standalone C++ static compute graph
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