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CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

The purpose of the repo is to support CORE-V Wally architectural verification

Functional verification project for the CORE-V family of RISC-V cores.

The purpose of the repo is to support CORE-V Wally architectural verification

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Functional verification project for the CORE-V family of RISC-V cores.

Changelog POC is a lightweight proof of concept designed to explore and validate the implementation of an automated changelog generation system

Aidge's learning module, written in C++, required for models training directly in Aidge

Aidge's C++ export module optimized for ARM Cortex-M

Aidge's reference C++ export module, required for generating standalone C++ static compute graph

Aidge's TensorRT export module. It act as a thin wrapper around NVidia's tools with easy custom operator insertion