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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Functional verification project for the CORE-V family of RISC-V cores.

Functional verification project for the CORE-V family of RISC-V cores.

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

Aidge's quantization module, for both PTQ and QAT, written in C++

Aidge's ONNX import/export module, written in Python, required for ONNX interoperability

Aidge's learning module, written in C++, required for models training directly in Aidge

Aidge's TensorRT export module. It act as a thin wrapper around NVidia's tools with easy custom operator insertion

Aidge's reference C++ export module, required for generating standalone C++ static compute graph

Aidge's C++ export module optimized for ARM Cortex-M

Aidge's core module, written in C++, always required

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Aidge's reference CPU backend, written in C++, not optimized for performances

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.