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4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Oniro Project

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Aidge's core module, written in C++, always required

Aidge export using Google XNNPACK library, which can be mixed with other C/C++ Aidge exports

The source of the asciidoc.org site, the entry point into the AsciiDoc ecosystem.

The Science Working Group (SWG) works to solve the problems of making science software inter-operable and interchangeable.

This toolset is responsible for synchronizing committers, contributors and settings across all Eclipse Foundation GitHub repositories and organizations.

Titan ProtocolModules L2TP

This project maintains the official specification, Technology Compatiblity Kit (TCK), and documentation for the AsciiDoc language and its APIs. The AsciiDoc Language Specification describes the syntax, grammar, and APIs for the AsciiDoc language.