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Documentation for the OpenHW Group's set of CORE-V RISC-V cores

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

CORE-V MCU DevKit drivers written with AWS CommonIO approach

4 stage, in-order, secure RISC-V core based on the CV32E40P

Aidge's reference CPU backend, written in C++, not optimized for performances

This project maintains the official specification, Technology Compatiblity Kit (TCK), and documentation for the AsciiDoc language and its APIs. The AsciiDoc Language Specification describes the syntax, grammar, and APIs for the AsciiDoc language.

The Eclipse Foundation provides our global community of individuals and organizations with a mature, scalable, and business-friendly environment for open source software collaboration and innovation.

OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices.

Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Common libraries, helpers, and wrappers used in the regular development of APIs at the Eclipse Foundation. This helps standardize operations and make downstream fixes easier.

Aidge's CUDA backend, written in C++/CUDA and using NVidia's CuDNN and CuBLAS libraries. Required for training and inference on NVidia's GPUs

Aidge's reference CPU backend, written in C++, not optimized for performances

Example SDK applications for DevKit

CVA6 SDK containing RISC-V tools and Buildroot

Advanced Verification Methodologies for RISC-V and related IP

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)