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CVA6 SDK containing RISC-V tools and Buildroot

Functional verification project for the CORE-V family of RISC-V cores.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Instruction Set Generator initially contributed by Futurewei

Deployment scripts for H3NI (including infrastructure), using PyInfra.

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

Titan Project

The HDAG and source of the customer dashboard.

Oniro Project Documentation

Aidge's reference C++ export module, required for generating standalone C++ static compute graph

Oniro Project Documentation

Tools for Software Composition Analysis

Functional verification project for the CORE-V family of RISC-V cores.