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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

OpenEmbedded layer for building OpenHarmony images and components.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Read-only wrapper library for OSI (ASAM Open Simulation Interface) to provide easy access to data even in aggregated form

The purpose of the repo is to support CORE-V Wally architectural verification

The Eclipse sim@openPASS platform mainly consists of a GUI and a simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Unofficial development fork of U-Boot

4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions

Eclipse/FreeRTOS/core-v-mcu example program

3rd party: Fork of https://git.yoctoproject.org/linux-yocto

The subproject opSimulation mainly consists of the simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/automotive.openpass

Eclipse ESCET project main repository.