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CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CV32E40X Design-Verification environment

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Instruction Set Generator initially contributed by Futurewei

Main Repo for the OpenHW Group Software Task Group

CVA6 SDK containing RISC-V tools and Buildroot

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge's quantization module, for both PTQ and QAT, written in C++

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

CVA6 SDK containing RISC-V tools and Buildroot

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

Functional verification project for the CORE-V family of RISC-V cores.

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Library for loading and providing data from an OpenDRIVE map

CORE-V Family of RISC-V Cores

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

CORE-V MCU DevKit drivers written with AWS CommonIO approach