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This project maintains the official specification, Technology Compatiblity Kit (TCK), and documentation for the AsciiDoc language and its APIs. The AsciiDoc Language Specification describes the syntax, grammar, and APIs for the AsciiDoc language.

This project maintains the official specification, Technology Compatiblity Kit (TCK), and documentation for the AsciiDoc language and its APIs. The AsciiDoc Language Specification describes the syntax, grammar, and APIs for the AsciiDoc language.

3rd party: Fork of https://github.com/kraj/meta-clang

Fork of Eclipse AIDGE export SONNX project

Linux kernel source tree

Get involved in Eclipse projects to help contribute to their success. We welcome users and adopters as part of the community.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

CV32E40X Design-Verification environment

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Instruction Set Generator initially contributed by Futurewei

Main Repo for the OpenHW Group Software Task Group

CVA6 SDK containing RISC-V tools and Buildroot

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

GT-Gen Core library which accepts ScenarioEngine, Environment and simulation parameters and enables the integrator to execute the simulation.

Aidge's quantization module, for both PTQ and QAT, written in C++

CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform

CVA6 SDK containing RISC-V tools and Buildroot

OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provides infrastructure to host high-quality open-source hardware projects aligned with industry best practices.

Functional verification project for the CORE-V family of RISC-V cores.