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Aidge export to ARM Tensor Operator Set Architecture (TOSA) format

Aidge meta-repository, which includes the main modules of the Aidge framework as Git submodules, plus the documentation and tutorials.

The Eclipse sim@openPASS platform mainly consists of a GUI and a simulation core interacting with openPASS modules as well as external programs for post-processing. https://projects.eclipse.org/projects/technology.simopenpass

4 stage, in-order, compute RISC-V core based on the CV32E40P

Graphene installation and maintenance scripts

The Eclipse® IDE Working Group is formed to ensure the continued sustainability, integrity, evolution, and adoption of the Eclipse IDE suite of products and related technologies.

fork of Eclipse Ease project

The OpenPiton Platform

Small and simple APB interrupt controller

Functional verification project for the CORE-V family of RISC-V cores.

The purpose of the repo is to support CORE-V Wally architectural verification

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

Aidge's reference CPU backend, written in C++, not optimized for performances

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.