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RTL code for implementation of dual-core trusted MCU

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.

CORE-V MCU DevKit drivers written with AWS CommonIO approach

Issues related to the OpenHW Group infra (GtHub, Mattermost, ...)

Functional verification project for the CORE-V family of RISC-V cores.

This project maintains the official specification, Technology Compatiblity Kit (TCK), and documentation for the AsciiDoc language and its APIs. The AsciiDoc Language Specification describes the syntax, grammar, and APIs for the AsciiDoc language.