Inconsistent assigment handling
Submitted by G??bor Szalai
Link to original bug (#492432)
Description
module proba{
type record R1{ integer i1, integer i2, integer i3 }
type component CT {}
testcase TC() runs on CT{ var R1 vl_r1:={1,2,3}
log(vl_r1) // { i1 := 1, i2 := 2, i3 := 3 }
vl_r1 :={ i2:=3 }
log(vl_r1) // { i1 := 1, i2 := 3, i3 := 3 }
vl_r1 :={ i1:=vl_r1.i2 }
log(vl_r1) // { i1 := 3, i2 := <unbound>
, i3 := <unbound>
}
// shuld be: { i1 := 3, i2 := 3, i3 := 3 }
}
control{ execute(TC()) }
}
Version: 5.4.0