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Commit 201ec6f9 authored by Terry Zhou's avatar Terry Zhou Committed by Greg Kroah-Hartman
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clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9


commit 6f37689c upstream.

There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: default avatarTerry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: default avatarPali Rohár <pali@kernel.org>
Fixes: 7ea82504 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org


Reviewed-by: default avatarMarek Behún <kabel@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent dcbda41a
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