yocto: import of the kernel content/metadata from v2.6.39

Roughly corresponds to:

    commit db575247e16e50ce5160e18907e253c6a43b6feb
    Author: Bruce Ashfield <bruce.ashfield@windriver.com>
    Date:   Mon Apr 4 00:27:55 2011 -0400

        yocto: 2.6.39 baseline

Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>

...in the full history repo, but with some extraneous files that were
deleted post db575247 deleted right here and now at the baseline
instead.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

00-README

+
+This is the cache of the kernel patches for the "next" kernel layer.
+

arch/arm/arm-ARM-EABI-socketcall.patch

+From 5fd6756ae2399b8e7bfc7489ed2f96fa8894d921 Mon Sep 17 00:00:00 2001
+From: Mark Asselstine <mark.asselstine@windriver.com>
+Date: Tue, 15 Jul 2008 15:49:27 -0400
+Subject: [PATCH 1/4] arm: ARM EABI socketcall
+
+This patch make that the sys_socketcall system call is available when
+EABI is used. The reason is that the user-space applications in both
+glibc_std rootfs and glibc_small rootfs are still using sys_socketcall
+to request kernel service.
+
+Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
+---
+ arch/arm/kernel/entry-common.S |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
+index 2c1db77..62ba415 100644
+--- a/arch/arm/kernel/entry-common.S
++++ b/arch/arm/kernel/entry-common.S
+@@ -329,7 +329,8 @@ __cr_alignment:
+  * With EABI a couple syscalls are obsolete and defined as sys_ni_syscall.
+  */
+ #define ABI(native, compat) native
+-#ifdef CONFIG_AEABI
++
++#if defined(CONFIG_AEABI) && !defined(CONFIG_OABI_COMPAT)
+ #define OBSOLETE(syscall) sys_ni_syscall
+ #else
+ #define OBSOLETE(syscall) syscall
+-- 
+1.6.5.2
+

arch/arm/arm.cfg

+# Build EABI kernels that support EABI system calls.
+CONFIG_AEABI=y
+
+# Provide support for the old ABI's system calls.
+CONFIG_OABI_COMPAT=y
+CONFIG_ARM_THUMB=y
+
+# Failure to use this on ARM results in lots of interesting runtime bugs.
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y

arch/arm/arm.scc

+# patches are for everyone, but the kconfig data is just for ARM builds.
+if [ "$WRS_ARCH" = "arm" ] || [ "$KARCH" = "arm" ]; then
+	kconf hardware arm.cfg
+fi
+
+patch arm-ARM-EABI-socketcall.patch

arch/mips/4kc-cache-tlb-hazard-tlbp-cache-coherency.patch

+From 09c63dde5c4a2430bc1f15eebe76de1ca357f175 Mon Sep 17 00:00:00 2001
+From: Weixing Shi <weixing.shi@windriver.com>
+Date: Mon, 12 Apr 2010 14:59:38 +0800
+Subject: [PATCH 3/8] 4kc cache tlb hazard: tlbp cache coherency
+
+Add a no-op before tlbp, to avoid DMA cache coherency issues that cause
+data loss seen on unmount.
+
+Signed-off-by: <weixing.shi@windriver.com> Weixing Shi
+Signed-off-by: <james.perkins@windriver.com> James Perkins
+---
+ arch/mips/mm/tlbex.c |    3 ++-
+ 1 files changed, 2 insertions(+), 1 deletions(-)
+
+diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
+index 0de0e41..e12b9bd 100644
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -244,6 +244,7 @@ static void __cpuinit __maybe_unused build_tlb_probe_entry(u32 **p)
+ 	case CPU_R5000:
+ 	case CPU_R5000A:
+ 	case CPU_NEVADA:
++	case CPU_4KC:
+ 		uasm_i_nop(p);
+ 		uasm_i_tlbp(p);
+ 		break;
+@@ -299,6 +300,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
+ 	case CPU_R4700:
+ 	case CPU_R5000:
+ 	case CPU_R5000A:
++	case CPU_4KC:
+ 		uasm_i_nop(p);
+ 		tlbw(p);
+ 		uasm_i_nop(p);
+@@ -315,7 +317,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
+ 	case CPU_R10000:
+ 	case CPU_R12000:
+ 	case CPU_R14000:
+-	case CPU_4KC:
+ 	case CPU_4KEC:
+ 	case CPU_SB1:
+ 	case CPU_SB1A:
+-- 
+1.6.5.2
+

arch/mips/malta-uhci-quirks-make-allowance-for-slow-4k-e-c.patch

+From 5513876234130f603b26e3d5788624f182e73d9e Mon Sep 17 00:00:00 2001
+From: Weixing Shi <weixing.shil@windriver.com>
+Date: Mon, 12 Apr 2010 14:58:03 +0800
+Subject: [PATCH 2/8] malta uhci quirks: make allowance for slow 4k(e)c
+
+This works around an unexpected IRQ #255 seen during initial USB host
+mass storage device initialization and access.
+* wait up to 50us for HCRESET to clear, a slow 4kc needs a longer time.
+* leave FSBR enabled so that a slow 4kec/24kec will not be overwhelmed.
+
+Signed-off-by: <weixing.shil@windriver.com> Weixing Shi
+Signed-off-by: <bruce.ashfield@windriver.com> Bruce Ashfield
+---
+ drivers/usb/host/pci-quirks.c |   14 ++++++++++++--
+ drivers/usb/host/uhci-q.c     |    4 +++-
+ 2 files changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
+index 83b5f9c..e906252 100644
+--- a/drivers/usb/host/pci-quirks.c
++++ b/drivers/usb/host/pci-quirks.c
+@@ -59,6 +59,9 @@
+  */
+ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
+ {
++#ifdef CONFIG_MIPS_MALTA
++	int timeout = 10;
++#endif
+ 	/* Turn off PIRQ enable and SMI enable.  (This also turns off the
+ 	 * BIOS's USB Legacy Support.)  Turn off all the R/WC bits too.
+ 	 */
+@@ -72,9 +75,16 @@ void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
+ 	outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
+ 	mb();
+ 	udelay(5);
+-	if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
+-		dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
+ 
++#ifdef CONFIG_MIPS_MALTA
++	while (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) {
++	        if (--timeout < 0) {
++			dev_warn(&pdev->dev, "HCRESET timed out!\n");
++			break;
++		}
++		udelay(5);
++	}
++#endif
+ 	/* Just to be safe, disable interrupt requests and
+ 	 * make sure the controller is stopped.
+ 	 */
+diff --git a/drivers/usb/host/uhci-q.c b/drivers/usb/host/uhci-q.c
+index acd582c..36acd40 100644
+--- a/drivers/usb/host/uhci-q.c
++++ b/drivers/usb/host/uhci-q.c
+@@ -71,7 +71,9 @@ static void uhci_fsbr_off(struct uhci_hcd *uhci)
+ static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
+ {
+ 	struct urb_priv *urbp = urb->hcpriv;
+-
++#ifdef CONFIG_MIPS_MALTA
++       return;
++#endif
+ 	if (!(urb->transfer_flags & URB_NO_FSBR))
+ 		urbp->fsbr = 1;
+ }
+-- 
+1.6.5.2
+

arch/mips/mips-support-preemptible-kernel.patch

+From 68feca2df43be3448b959f915e969d6ec49be5b2 Mon Sep 17 00:00:00 2001
+From: Tiejun Chen <tiejun.chen@windriver.com>
+Date: Mon, 12 Apr 2010 15:03:02 +0800
+Subject: [PATCH 4/8] mips support preemptible kernel
+
+Some warning message result from calling function, smp_processor_id(),
+if enable preempt option. So we should do explicitly somewhere when running
+preemptible kernel, especially for some cache operation.
+
+Signed-off-by: Tiejun Chen <tiejun.chen@windriver.com>
+---
+ arch/mips/kernel/proc.c |    6 ++++--
+ arch/mips/mm/c-r4k.c    |    8 ++++----
+ 2 files changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
+index 26109c4..ed15fa8 100644
+--- a/arch/mips/kernel/proc.c
++++ b/arch/mips/kernel/proc.c
+@@ -21,7 +21,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
+ 	unsigned int version = cpu_data[n].processor_id;
+ 	unsigned int fp_vers = cpu_data[n].fpu_id;
+ 	char fmt [64];
+-	int i;
++	int cpu,i;
+ 
+ #ifdef CONFIG_SMP
+ 	if (!cpu_isset(n, cpu_online_map))
+@@ -37,9 +37,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
+ 	seq_printf(m, "processor\t\t: %ld\n", n);
+ 	sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
+ 	        cpu_data[n].options & MIPS_CPU_FPU ? "  FPU V%d.%d" : "");
+-	seq_printf(m, fmt, __cpu_name[n],
++	cpu = get_cpu();
++	seq_printf(m, fmt, __cpu_name[cpu],
+ 	                           (version >> 4) & 0x0f, version & 0x0f,
+ 	                           (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
++	put_cpu();
+ 	seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
+ 	              cpu_data[n].udelay_val / (500000/HZ),
+ 	              (cpu_data[n].udelay_val / (5000/HZ)) % 100);
+diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
+index 6721ee2..898f8ec 100644
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -383,12 +383,12 @@ static inline int has_valid_asid(const struct mm_struct *mm)
+ 
+ static void r4k__flush_cache_vmap(void)
+ {
+-	r4k_blast_dcache();
++	r4k_on_each_cpu((void *)r4k_blast_dcache, NULL);
+ }
+ 
+ static void r4k__flush_cache_vunmap(void)
+ {
+-	r4k_blast_dcache();
++	r4k_on_each_cpu((void *)r4k_blast_dcache, NULL);
+ }
+ 
+ static inline void local_r4k_flush_cache_range(void * args)
+@@ -614,7 +614,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+ 	 * explicitly
+ 	 */
+ 	if (cpu_has_safe_index_cacheops && size >= dcache_size) {
+-		r4k_blast_dcache();
++		r4k_on_each_cpu((void *)r4k_blast_dcache, NULL);
+ 	} else {
+ 		R4600_HIT_CACHEOP_WAR_IMPL;
+ 		blast_dcache_range(addr, addr + size);
+@@ -652,7 +652,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
+ 	}
+ 
+ 	if (cpu_has_safe_index_cacheops && size >= dcache_size) {
+-		r4k_blast_dcache();
++		r4k_on_each_cpu((void *)r4k_blast_dcache, NULL);
+ 	} else {
+ 		unsigned long lsize = cpu_dcache_line_size();
+ 		unsigned long almask = ~(lsize - 1);
+-- 
+1.6.5.2
+

arch/mips/mips.scc

+patch malta-uhci-quirks-make-allowance-for-slow-4k-e-c.patch
+patch 4kc-cache-tlb-hazard-tlbp-cache-coherency.patch
+patch mips-support-preemptible-kernel.patch
+# merged to mainline in 2.6.34
+# patch BCM1250-M3-workaround-fix.patch
+#patch fix-support-for-SMTC-on-Malta-34Kc.patch
+#patch mips-cavium-return-correct-sockopt-size-for-n32-on-6.patch
+#patch Enable-kernel-snapshots.patch
+#patch Perf-tool-MIPS-support-cross-compiling-of-tools-perf.patch
+#patch tracing-MIPS-mcount.S-merge-the-same-continuous-ifde.patch
+#patch tracing-MIPS-mcount.S-cleanup-the-arguments-of-prepa.patch
+#patch tracing-MIPS-mcount.S-cleanup-of-the-comments.patch
+#patch tracing-MIPS-mcount.S-Fix-the-argument-passing-of-th.patch
+#patch tracing-MIPS-Fixup-of-the-32bit-support-with-mmcount.patch
+#patch tracing-MIPS-cleanup-of-the-instructions.patch
+#patch tracing-MIPS-Reduce-the-overhead-of-dynamic-Function.patch
+#patch tracing-MIPS-cleanup-of-function-graph-tracer.patch
+#patch tracing-MIPS-cleanup-of-the-address-space-checking.patch
+#patch MIPS-Audit-Fix-hang-when-starting-audit.patch

arch/powerpc/powerpc-85xx-Make-sure-lwarx-hint-isn-t-set-on-ppc32.patch

+From 3bfd2e49b772405748e319a886447bbb0bb7fe06 Mon Sep 17 00:00:00 2001
+From: Kumar Gala <galak@kernel.crashing.org>
+Date: Wed, 10 Mar 2010 23:39:07 -0600
+Subject: [PATCH] powerpc/85xx: Make sure lwarx hint isn't set on ppc32
+
+e500v1/v2 based chips will treat any reserved field being set in an
+opcode as illegal.  Thus always setting the hint in the opcode is
+a bad idea.
+
+Anton should be kept away from the powerpc opcode map.
+
+Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
+---
+ arch/powerpc/include/asm/ppc-opcode.h |    6 +++---
+ 1 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
+index aea7147..d553bbe 100644
+--- a/arch/powerpc/include/asm/ppc-opcode.h
++++ b/arch/powerpc/include/asm/ppc-opcode.h
+@@ -25,7 +25,7 @@
+ #define PPC_INST_LDARX			0x7c0000a8
+ #define PPC_INST_LSWI			0x7c0004aa
+ #define PPC_INST_LSWX			0x7c00042a
+-#define PPC_INST_LWARX			0x7c000029
++#define PPC_INST_LWARX			0x7c000028
+ #define PPC_INST_LWSYNC			0x7c2004ac
+ #define PPC_INST_LXVD2X			0x7c000698
+ #define PPC_INST_MCRXR			0x7c000400
+@@ -62,8 +62,8 @@
+ #define __PPC_T_TLB(t)	(((t) & 0x3) << 21)
+ #define __PPC_WC(w)	(((w) & 0x3) << 21)
+ /*
+- * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
+- * any side effects on all 32bit processors, we can do this all the time.
++ * Only use the larx hint bit on 64bit CPUs. e500v1/v2 based CPUs will treat a
++ * larx with EH set as an illegal instruction.
+  */
+ #ifdef CONFIG_PPC64
+ #define __PPC_EH(eh)	(((eh) & 0x1) << 0)
+-- 
+1.6.5.2
+

arch/powerpc/powerpc-Add-unwind-information-for-SPE-registers-of-.patch

+From 87398e3c68b21d06817c44ca39449ef382d2ce31 Mon Sep 17 00:00:00 2001
+From: Liming Wang <liming.wang@windriver.com>
+Date: Fri, 19 Dec 2008 11:16:39 +0800
+Subject: [PATCH 1/3] powerpc: Add unwind information for SPE registers of E500 core
+
+SPE registers use the high part bit0~bit31 of E500 GPR0~GPR31.
+The unwind information in "eh_frame" section is used during exception
+handling and describes register information in the signal frame. But
+current unwind information doesn't cover SPE registers, which have
+been saved in the signal frame. This patch adds this unwind information
+to "eh_frame" section.
+
+SPE registers use register number 1200+N to identify register 'N', but
+they start from 113 in unwind column, which is computed from gcc
+source code, macro DWARF_REG_TO_UNWIND_COLUMN:
+
+	#define FIRST_PSEUDO_REGISTER 114
+	#define DWARF_REG_TO_UNWIND_COLUMN(r) \
+  	  ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
+
+Signed-off-by: Liming Wang <liming.wang@windriver.com>
+---
+ arch/powerpc/kernel/vdso32/sigtramp.S |   34 +++++++++++++++++++++++++++++++++
+ 1 files changed, 34 insertions(+), 0 deletions(-)
+
+diff --git a/arch/powerpc/kernel/vdso32/sigtramp.S b/arch/powerpc/kernel/vdso32/sigtramp.S
+index 68d49dd..789a343 100644
+--- a/arch/powerpc/kernel/vdso32/sigtramp.S
++++ b/arch/powerpc/kernel/vdso32/sigtramp.S
+@@ -251,6 +251,40 @@ V_FUNCTION_END(__kernel_sigtramp_rt32)
+   vsave_msr1 (31);							\
+   vsave_msr2 (33, 32*16+12);						\
+   vsave      (32, 32*16)
++#elif defined(CONFIG_SPE)
++#define EH_FRAME_VMX \
++  rsave (113, VREGS);							\
++  rsave (114, VREGS + 1*4);						\
++  rsave (115, VREGS + 2*4);						\
++  rsave (116, VREGS + 3*4);						\
++  rsave (117, VREGS + 4*4);						\
++  rsave (118, VREGS + 5*4);						\
++  rsave (119, VREGS + 6*4);						\
++  rsave (120, VREGS + 7*4);						\
++  rsave (121, VREGS + 8*4);						\
++  rsave (122, VREGS + 9*4);						\
++  rsave (123, VREGS + 10*4);						\
++  rsave (124, VREGS + 11*4);						\
++  rsave (125, VREGS + 12*4);						\
++  rsave (126, VREGS + 13*4);						\
++  rsave (127, VREGS + 14*4);						\
++  rsave (128, VREGS + 15*4);						\
++  rsave (129, VREGS + 16*4);						\
++  rsave (130, VREGS + 17*4);						\
++  rsave (131, VREGS + 18*4);						\
++  rsave (132, VREGS + 19*4);						\
++  rsave (133, VREGS + 20*4);						\
++  rsave (134, VREGS + 21*4);						\
++  rsave (135, VREGS + 22*4);						\
++  rsave (136, VREGS + 23*4);						\
++  rsave (137, VREGS + 24*4);						\
++  rsave (138, VREGS + 25*4);						\
++  rsave (139, VREGS + 26*4);						\
++  rsave (140, VREGS + 27*4);						\
++  rsave (141, VREGS + 28*4);						\
++  rsave (142, VREGS + 29*4);						\
++  rsave (143, VREGS + 30*4);						\
++  rsave (144, VREGS + 31*4);
+ #else
+ #define EH_FRAME_VMX
+ #endif
+-- 
+1.6.5.2
+

arch/powerpc/powerpc-add-crtsavres.o-to-archprepare-for-kbuild.patch

+From f13fd6af4120b8b42d77377c9989457cda41899f Mon Sep 17 00:00:00 2001
+From: Bruce Ashfield <bruce.ashfield@windriver.com>
+Date: Sun, 15 Feb 2009 16:57:14 -0500
+Subject: [PATCH 3/3] powerpc: add crtsavres.o to archprepare for kbuild
+
+upstream commit da3de6df33f5f42ff9dc40093fbc884f524c9a49 adds
+a dependency to all kernel modules to crtsavres. This
+ensures that out-of-line register saves/restores work when
+CONFIG_CC_OPTIMIZE_FOR_SIZE is enabled.
+
+What it didn't do was ensure that it was built when
+modules_prepare was run and hence out of tree powerpc kernel
+modules can't properly link.
+
+The fix is to add crtsavres.o to the archprepare rule in
+the arch/powerpc/Makefile
+
+Signed-off-by: Bruce Ashfield <bruce.ashfield@windriver.com>
+---
+ arch/powerpc/Makefile |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
+index c3811ab..ad16ff3 100644
+--- a/arch/powerpc/Makefile
++++ b/arch/powerpc/Makefile
+@@ -218,7 +218,7 @@ endif
+ archclean:
+ 	$(Q)$(MAKE) $(clean)=$(boot)
+ 
+-archprepare: checkbin
++archprepare: checkbin arch/powerpc/lib/crtsavres.o
+ 
+ # Use the file '.tmp_gas_check' for binutils tests, as gas won't output
+ # to stdout and these checks are run even on install targets.
+-- 
+1.6.5.2
+

arch/powerpc/powerpc-kexec-fix-for-powerpc64.patch

+From 47053669db2f9f6eefc678a0afbb28e14bfc1dfc Mon Sep 17 00:00:00 2001
+From: Benjamin Walsh <benjamin.walsh@windriver.com>
+Date: Mon, 9 Feb 2009 14:25:47 -0500
+Subject: [PATCH 2/3] powerpc: kexec fix for powerpc64
+
+slbia instruction invalidates the SLB, but there was a hang on the first
+instruction that caused an SLB miss exception. Doing a full sync after
+the slbia causes the SLB to be in a consistent state for the handling of
+the SLB exception.
+
+Signed-off by: Benjamin Walsh <benjamin.walsh@windriver.com>
+---
+ arch/powerpc/mm/slb.c |    1 +
+ 1 files changed, 1 insertions(+), 0 deletions(-)
+
+diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
+index 1d98ecc..e982190 100644
+--- a/arch/powerpc/mm/slb.c
++++ b/arch/powerpc/mm/slb.c
+@@ -319,6 +319,7 @@ void slb_initialize(void)
+ 	asm volatile("isync":::"memory");
+ 	asm volatile("slbmte  %0,%0"::"r" (0) : "memory");
+ 	asm volatile("isync; slbia; isync":::"memory");
++	mb();
+ 	create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, 0);
+ 
+ 	create_shadowed_slbe(VMALLOC_START, mmu_kernel_ssize, vflags, 1);
+-- 
+1.6.5.2
+

arch/powerpc/powerpc.scc

+patch powerpc-Add-unwind-information-for-SPE-registers-of-.patch
+patch powerpc-kexec-fix-for-powerpc64.patch
+patch powerpc-add-crtsavres.o-to-archprepare-for-kbuild.patch

bsp/arm-versatile-926ejs/arm-versatile-926ejs-gfx.cfg

+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+
+CONFIG_INPUT_TABLET=y
+CONFIG_TABLET_USB_WACOM=y
+CONFIG_INPUT_MISC=y
+

bsp/arm-versatile-926ejs/arm-versatile-926ejs-standard.scc

+define KMACHINE arm-versatile-926ejs
+define KTYPE standard
+define KARCH arm
+
+scc_leaf ktypes/standard arm-versatile-926ejs
+
+
+include arm-versatile-926ejs.scc
+

bsp/arm-versatile-926ejs/arm-versatile-926ejs.cfg

+..........................................................................
+.                                WARNING
+.
+. This file is a kernel configuration fragment, and not a full kernel
+. configuration file.  The final kernel configuration is made up of
+. an assembly of processed fragments, each of which is designed to
+. capture a specific part of the final configuration (e.g. platform
+. configuration, feature configuration, and board specific hardware
+. configuration).  For more information on kernel configuration, please
+. consult the product documentation.
+.
+..........................................................................
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_ARCH_VERSATILE=y
+CONFIG_VFP=y
+CONFIG_ARCH_VERSATILE_PB=y
+CONFIG_MACH_VERSATILE_PB=y
+# CONFIG_MACH_VERSATILE_AB is not set
+
+# CONFIG_PHYLIB is not set
+CONFIG_MII=y
+CONFIG_SMC91X=y
+
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_ARM_INTEGRATOR=y
+
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_AMBA_PL011=y
+
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_ARMMMCI=y
+
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+
+CONFIG_PCI=y
+
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SYM53C8XX_2=y
+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
+CONFIG_SCSI_SYM53C8XX_MMIO=y
+
+
+CONFIG_SERIO=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_INPUT_EVDEV=y
+
+CONFIG_LATENCYTOP=y
+
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_FRAME_POINTER=y
+CONFIG_X86_UP_APIC=y
+CONFIG_X86_LOCAL_APIC=y
+
+CONFIG_TIMER_STATS=y
+
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_HPET_TIMER=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_USB_SUSPEND=y
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_TIMER_STATS=y

bsp/arm-versatile-926ejs/arm-versatile-926ejs.scc

+kconf hardware arm-versatile-926ejs.cfg
+kconf hardware arm-versatile-926ejs-gfx.cfg
+
+patch arm_versatile_926ejs-add-default-nor-flash-mtd-parts.patch
+patch arm_versatile_926ejs-kick-off-PrimeCell-RTC-PL031.patch

bsp/arm-versatile-926ejs/arm_versatile_926ejs-add-default-nor-flash-mtd-parts.patch

+From 95bc50e18b33b8373193294bc39cbdf066d27158 Mon Sep 17 00:00:00 2001
+From: bo liu <bliu0@pek-lpgbuild5.(none)>
+Date: Wed, 24 Feb 2010 01:33:11 -0800
+Subject: [PATCH 1/2] arm_versatile_926ejs: add default nor flash mtd parts
+
+Create default MTD partition tables for versatile and fix the problem
+that without partition the integrator map driver will fail to register
+mtd device.
+
+Signed-off-by: Tony Liu <Bo.Liu@windriver.com>
+---
+ arch/arm/mach-versatile/core.c      |   33 +++++++++++++++++++++++++++++++++
+ drivers/mtd/maps/integrator-flash.c |   13 ++++++++-----
+ 2 files changed, 41 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
+index e13be7c..42f8bf0 100644
+--- a/arch/arm/mach-versatile/core.c
++++ b/arch/arm/mach-versatile/core.c
+@@ -22,6 +22,8 @@
+ #include <linux/device.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/platform_device.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
+ #include <linux/sysdev.h>
+ #include <linux/interrupt.h>
+ #include <linux/amba/bus.h>
+@@ -284,12 +286,43 @@ static void versatile_flash_set_vpp(int on)
+ 	__raw_writel(val, VERSATILE_FLASHCTRL);
+ }
+ 
++static struct mtd_partition versatile_partitions[] = {
++	{ /* bootloader and params */
++		.name           = "bootloader",
++		.offset         = 0,
++		.size           = SZ_256K +  SZ_128K,
++		.mask_flags     = MTD_WRITEABLE,        /* force read-only */
++	}, {
++		.name           = "kernel",
++		.offset         = MTDPART_OFS_APPEND,
++		.size           = (0x400000 - 0x60000),
++		.mask_flags     = 0,
++	}, {
++		.name           = "jffs2",
++		.offset         = MTDPART_OFS_APPEND,
++		.size           = 0x700000,
++		.mask_flags     = 0,
++	}, {
++		.name           = "cramfs",
++		.offset         = MTDPART_OFS_APPEND,
++		.size           = 0x200000,
++		.mask_flags     = 0,
++	}, {
++		.name           = "user data",
++		.offset         = MTDPART_OFS_APPEND,
++		.size           = MTDPART_SIZ_FULL,
++		.mask_flags     = 0,
++	}
++};
++
+ static struct flash_platform_data versatile_flash_data = {
+ 	.map_name		= "cfi_probe",
+ 	.width			= 4,
+ 	.init			= versatile_flash_init,
+ 	.exit			= versatile_flash_exit,
+ 	.set_vpp		= versatile_flash_set_vpp,
++	.parts                  = versatile_partitions,
++	.nr_parts               = ARRAY_SIZE(versatile_partitions),
+ };
+ 
+ static struct resource versatile_flash_resource = {
+diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c
+index 2aac41b..11b9229 100644
+--- a/drivers/mtd/maps/integrator-flash.c
++++ b/drivers/mtd/maps/integrator-flash.c
+@@ -225,13 +225,16 @@ static int armflash_probe(struct platform_device *dev)
+ 	if (err < 0)
+ 		goto cleanup;
+ 
++#ifdef CONFIG_MTD_PARTITIONS
+ 	err = parse_mtd_partitions(info->mtd, probes, &info->parts, 0);
+-	if (err > 0) {
++	if (err > 0)
+ 		err = add_mtd_partitions(info->mtd, info->parts, err);
+-		if (err)
+-			printk(KERN_ERR
+-			       "mtd partition registration failed: %d\n", err);
+-	}
++	else if (err <= 0 && plat->parts)
++		err = add_mtd_partitions(info->mtd, plat->parts,
++			plat->nr_parts);
++	else
++#endif
++		err = add_mtd_device(info->mtd);
+ 
+ 	if (err == 0) {
+ 		platform_set_drvdata(dev, info);
+-- 
+1.6.5.2
+

bsp/arm-versatile-926ejs/arm_versatile_926ejs-kick-off-PrimeCell-RTC-PL031.patch

+From f0f58d065652e147f761739cbbcaf8de1b49baa3 Mon Sep 17 00:00:00 2001
+From: Tony Liu <Bo.Liu@windriver.com>
+Date: Thu, 25 Feb 2010 16:23:42 +0800
+Subject: [PATCH 2/2] arm_versatile_926ejs: kick off PrimeCell RTC PL031
+
+For RTC PL031, need to explicitly set bit "RTC start" of Control
+register(RTCCR) to enable it's counting.
+
+Signed-off-by: Tony Liu <Bo.Liu@windriver.com>
+---
+ drivers/rtc/rtc-pl031.c |    3 +++
+ 1 files changed, 3 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/rtc/rtc-pl031.c b/drivers/rtc/rtc-pl031.c
+index 0264b11..7009c49 100644
+--- a/drivers/rtc/rtc-pl031.c
++++ b/drivers/rtc/rtc-pl031.c
+@@ -163,6 +163,9 @@ static int pl031_probe(struct amba_device *adev, struct amba_id *id)
+ 		goto out_no_rtc;
+ 	}
+ 
++	/*Set bit "RTC start" in register RTCCR to enable RTC */
++	writel(0x1, ldata->base + RTC_CR);
++
+ 	return 0;
+ 
+ out_no_rtc:
+-- 
+1.6.5.2
+

bsp/atom-pc/atom-pc-eth.cfg

+CONFIG_R8169=y
+CONFIG_ATL1E=y