Merge requests · Eclipse Projects / Eclipse ESCET (Supervisory Control Engineering Toolkit) / escet · GitLab

#679 PLCgen: Give all [CifData]Provider functions and variables a "cifData" name.

!751 · created Jan 02, 2024 by Albert Hofkamp v3.0
CIF TypeEnhancement
- Merged
- Approved
updated Jan 18, 2024
#679 PLCgen: Forbid pure monitor events.

!839 · created Mar 22, 2024 by Albert Hofkamp v4.0
CIF TypeEnhancement
- Merged
- 24
- Approved
updated Mar 31, 2024
#679 PLCgen: Drop writing to the derivative of a continuous variable.

!1093 · created Oct 15, 2024 by Albert Hofkamp v6.0
CIF TypeEnhancement
- Merged
- 1
- Approved
updated Oct 15, 2024
#679 PLCgen: Disallow arrays of length 0.

!879 · created May 09, 2024 by Albert Hofkamp v4.0
CIF TypeEnhancement
- Merged
- Approved
updated May 09, 2024
#679 PLCgen: Cleanup and fix variable handling

!770 · created Jan 16, 2024 by Albert Hofkamp v3.0
CIF TypeEnhancement
- Merged
- 51
- Approved
updated Jan 23, 2024
#679 PLCgen: Avoid getting double underscore characters in generated names.

!806 · created Feb 13, 2024 by Albert Hofkamp v3.0
CIF TypeEnhancement
- Merged
- 14
- Approved
updated Feb 16, 2024
#679 PLCgen: Add constants support

!905 · created May 29, 2024 by Albert Hofkamp v4.0
CIF TypeEnhancement
- Merged
- 17
- Approved
updated Jun 10, 2024
#679 PLCgen: Add automatic enum conversion option.

!764 · created Jan 10, 2024 by Albert Hofkamp v3.0
CIF TypeEnhancement
- Merged
- 44
- Approved
updated Jan 18, 2024
#679 Make "timer" a reserved word in PLCgen

!920 · created Jun 10, 2024 by Albert Hofkamp v4.0
CIF TypeEnhancement
- Merged
- 1
- Approved
updated Jun 10, 2024
#679 Improve naming of tuple types in PLCgen

!1018 · created Aug 02, 2024 by Albert Hofkamp v5.0
CIF TypeEnhancement
- Merged
- 6
- Approved
updated Sep 26, 2024
#679 Add 'cifplcgen' to scriptable tools overview in CIF docs.

!731 · created Dec 21, 2023 by Dennis Hendriks v2.0
CIF TypeBug
- Merged
- 1
- Approved
updated Dec 21, 2023
#679 #860 PLCgen: Ensure that the main program always has a proper PLC statement.

!932 · created Jun 17, 2024 by Albert Hofkamp v4.0
CIF TypeBug
- Merged
- 7
- Approved
updated Jun 18, 2024
#678 Free dropped bits for CifBddBitVector resize.

!672 · created Oct 21, 2023 by Ferdie Reijnen v2.0
CIF TypeBug
- Merged
- 7
- Approved
updated Oct 24, 2023
#676 PLCgen: Forbid use of user-defined functions.

!689 · created Nov 10, 2023 by Albert Hofkamp v2.0
CIF TypeEnhancement
- Merged
- 3
- Approved
updated Nov 14, 2023
#676 PLCgen: Connect PLCgen with the GUI.

!690 · created Nov 10, 2023 by Albert Hofkamp v2.0
CIF TypeEnhancement
- Merged
- 28
- Approved
updated Nov 20, 2023
#676 PLCgen: Add documentation.

!700 · created Nov 24, 2023 by Albert Hofkamp v2.0
CIF TypeEnhancement
- Merged
- 346
- Approved
updated Dec 14, 2023
#676 Make 'plcgen' available from ToolDef

!674 · created Oct 26, 2023 by Albert Hofkamp v2.0
CIF TypeEnhancement
- Merged
- 9
- Approved
updated Oct 30, 2023
#676 Insert empty line between different event transitions

!697 · created Nov 20, 2023 by Albert Hofkamp v2.0
CIF TypeEnhancement
- Merged
- 27
- Approved
updated Nov 23, 2023
#675 PLCgen Siemens target: location variables get assigned non-existing values.

!682 · created Oct 31, 2023 by Albert Hofkamp v2.0
CIF TypeBug
- Merged
- 1
- Approved
updated Oct 31, 2023
#672 Improved CIF type checker messages for component definition/instantiation mismatch

!677 · created Oct 29, 2023 by Dennis Hendriks v2.0
CIF TypeEnhancement
- Merged
- 7
- Approved
updated Nov 13, 2023

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