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Commit a0dc9e6e authored by Cyril Moineau's avatar Cyril Moineau
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Adapt forward to output nodes of exports being pointer of pointer.

parent e5c99377
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3 merge requests!17v0.1.0,!12v0.4.0,!11Export refactor
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with 23 additions and 30 deletions
{% for outidx in range(nb_out) -%}
{{out_cdtype[outidx]}}* {{out_name[outidx]}} = ({{out_cdtype[outidx]}}*) mem + {{out_name[outidx]|upper}}_OFFSET;
{% endfor %}
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_add_float32( aidge_add_float32(
{{in_name[0]}}, {{in_name[0]}},
{{in_name[1]}}, {{in_name[1]}},
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_atan <{{name|upper}}_OUTPUTS_SIZE> ({{in_name[0]}}, {{out_name[0]}}); aidge_atan <{{name|upper}}_OUTPUTS_SIZE> ({{in_name[0]}}, {{out_name[0]}});
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
float* {{ name|upper }}_INPUTS[] = { float* {{ name|upper }}_INPUTS[] = {
{%- for i in range(nb_in) -%} {%- for i in range(nb_in) -%}
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
N2D2_Export::convcellPropagate<{{ in_name[0]|upper }}_NB_CHANNELS, N2D2_Export::convcellPropagate<{{ in_name[0]|upper }}_NB_CHANNELS,
{{ in_name[0]|upper }}_IN_HEIGHT, {{ in_name[0]|upper }}_IN_HEIGHT,
{{ in_name[0]|upper }}_IN_WIDTH, {{ in_name[0]|upper }}_IN_WIDTH,
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
N2D2_Export::fccellPropagate<{{ in_name[0] | upper }}_NB_CHANNELS, N2D2_Export::fccellPropagate<{{ in_name[0] | upper }}_NB_CHANNELS,
{{ in_name[0] | upper }}_IN_HEIGHT, {{ in_name[0] | upper }}_IN_HEIGHT,
{{ in_name[0] | upper }}_IN_WIDTH, {{ in_name[0] | upper }}_IN_WIDTH,
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_mul_float32( aidge_mul_float32(
{{in_name[0]}}, {{in_name[0]}},
{{in_name[1]}}, {{in_name[1]}},
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
N2D2_Export::poolcellPropagate<{{ in_name[0]|upper }}_NB_CHANNELS, N2D2_Export::poolcellPropagate<{{ in_name[0]|upper }}_NB_CHANNELS,
{{ in_name[0]|upper }}_IN_HEIGHT, {{ in_name[0]|upper }}_IN_HEIGHT,
{{ in_name[0]|upper }}_IN_WIDTH, {{ in_name[0]|upper }}_IN_WIDTH,
......
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_relu_float32({{in_name[0]}}, {{out_name[0]}}, {{name|upper}}_INPUTS_SIZE); aidge_relu_float32({{in_name[0]}}, {{out_name[0]}}, {{name|upper}}_INPUTS_SIZE);
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_slice_float32 ({{in_name[0]}}, {{out_name[0]}}, {{name|upper}}_AXES, {{name|upper}}_STARTS, {{name|upper}}_ENDS, {{name|upper}}_NB_AXES, {{name|upper}}_NB_CHANNELS); aidge_slice_float32 ({{in_name[0]}}, {{out_name[0]}}, {{name|upper}}_AXES, {{name|upper}}_STARTS, {{name|upper}}_ENDS, {{name|upper}}_NB_AXES, {{name|upper}}_NB_CHANNELS);
{% if not is_output %} {% include "./_mem_offset.jinja" %}
{{out_cdtype[0]}}* {{out_name[0]}} = ({{out_cdtype[0]}}*) mem + {{out_name[0]|upper}}_OFFSET;
{% endif %}
aidge_sub_float32({{in_name[0]}}, {{in_name[1]}}, {{out_name[0]}}, {{name|upper}}_OUTPUTS_SIZE); aidge_sub_float32({{in_name[0]}}, {{in_name[1]}}, {{out_name[0]}}, {{name|upper}}_OUTPUTS_SIZE);
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