Low bit support for ARM Cortex-M export

• Add aidge types (type not compressed & type compressed)
  • int4 (. . . . v v v v) & dual_int4 (v v v v v v v v)
  • int3 (. . . . . v v v) & dual_int3 (. v v v . v v v)
  • int2 & quad_int2
  • uint4 & dual_uint4
  • uint3 & dual_uint3
  • uint2 & quad_uint2
  • binary & octo_binary
• Each aidge type uses a std::int8_t or std::uint8_t (for aide tensor, tensor binding to numpy,...)
• Add operator WeightInterleaving that compact tensor data on the last dimension of the Tensor. It requires input tensor format NHWC because the implemented kernels in ARM Cortex-M are HWC.
• Python binding of Operator WeightInterleaving and ApplyWeightInterleaving recipe
• Adapt data_convertion to a generic function taking a data conversionmap as input and integrate it into nodeExport. Each nodeExport instanciation in the export operator registry can specify a different data conversion map (from aidge to export type).

Closes : aidge_export_arm_cortexm#22 (closed)

include/aidge/utils/DynamicAttributes.hpp

@@ -445,6 +445,17 @@ namespace std {
             return seed;
         }
     };
+
+    // Specialization of std::hash for std::pair<T1, T2>
+    template <typename T1, typename T2>
+    struct hash<std::pair<T1, T2>> {
+        std::size_t operator()(const std::pair<T1, T2>& p) const {
+            std::size_t seed = 0;
+            Aidge::hash_combine(seed, std::hash<T1>()(p.first));
+            Aidge::hash_combine(seed, std::hash<T2>()(p.second));
+            return seed;
+        }
+    };
 }
 
 namespace future_std {