Scheduler ConnectInput and tensor filling with offset tests

Tests of Scheduler::connectInputs

The function Scheduler::connectInputs was added in aidge core in /aidge/aidge_core!4. This function use graph ordering to connect the inputs of a graphView to data Tensors passed in a Scheduler::forward.

• Add Scheduler::connectInputs tests

Test batch composition in a tensor

• Add test to fill tensor with offset (for batch composition)

Add registrar support for more DataTypes in tensor for backend_cpu

• Add more TensorImpl backend_cpu DataType coverage

Adapt the tensorImpl_cpu class constructor to respect the mother class TensorImpl

In this MR the constructor of TensorImpl_cpu is adapted to the new definition of TensorImpl. The TensorImpl mother class constructor was modified in /aidge/aidge_core!4. The mother class modification was meant to adapt the TensorImpl for backend opencv.

• Change number of elements for dims in TensorImpl

include/aidge/backend/cpu/data/TensorImpl.hpp

@@ -33,7 +33,7 @@ private:
 public:
     static constexpr const char *Backend = "cpu";
 
-    TensorImpl_cpu(DeviceIdx_t device, NbElts_t length) : TensorImpl(Backend, device, length) {}
+    TensorImpl_cpu(DeviceIdx_t device, std::vector<DimSize_t> dims) : TensorImpl(Backend, device, dims) {}
 
     bool operator==(const TensorImpl &otherImpl) const override final {
         const auto& typedOtherImpl = reinterpret_cast<const TensorImpl_cpu<T> &>(otherImpl);
@@ -47,8 +47,8 @@ public:
         return i == mNbElts;
     }
 
-    static std::shared_ptr<TensorImpl_cpu> create(DeviceIdx_t device, NbElts_t length) {
-        return std::make_shared<TensorImpl_cpu<T>>(device, length);
+    static std::shared_ptr<TensorImpl_cpu> create(DeviceIdx_t device, std::vector<DimSize_t> dims) {
+        return std::make_shared<TensorImpl_cpu<T>>(device, dims);
     }
 
     inline std::size_t scalarSize() const noexcept override final { return sizeof(T); }
@@ -175,7 +175,6 @@ private:
         }
     }
 };
-
 namespace {
 static Registrar<Tensor> registrarTensorImpl_cpu_Float64(
         {"cpu", DataType::Float64}, Aidge::TensorImpl_cpu<double>::create);
@@ -183,10 +182,18 @@ static Registrar<Tensor> registrarTensorImpl_cpu_Float32(
         {"cpu", DataType::Float32}, Aidge::TensorImpl_cpu<float>::create);
 static Registrar<Tensor> registrarTensorImpl_cpu_Float16(
         {"cpu", DataType::Float16}, Aidge::TensorImpl_cpu<half_float::half>::create);
-static Registrar<Tensor> registrarTensorImpl_cpu_Int32(
-        {"cpu", DataType::Int32}, Aidge::TensorImpl_cpu<int>::create);
 static Registrar<Tensor> registrarTensorImpl_cpu_Int64(
         {"cpu", DataType::Int64}, Aidge::TensorImpl_cpu<long>::create);
+static Registrar<Tensor> registrarTensorImpl_cpu_Int32(
+        {"cpu", DataType::Int32}, Aidge::TensorImpl_cpu<int>::create);
+static Registrar<Tensor> registrarTensorImpl_cpu_Int16(
+        {"cpu", DataType::Int16}, Aidge::TensorImpl_cpu<int16_t>::create);
+static Registrar<Tensor> registrarTensorImpl_cpu_UInt16(
+        {"cpu", DataType::UInt16}, Aidge::TensorImpl_cpu<uint16_t>::create);
+static Registrar<Tensor> registrarTensorImpl_cpu_Int8(
+        {"cpu", DataType::Int8}, Aidge::TensorImpl_cpu<int8_t>::create);
+static Registrar<Tensor> registrarTensorImpl_cpu_UInt8(
+        {"cpu", DataType::UInt8}, Aidge::TensorImpl_cpu<uint8_t>::create);
 }  // namespace
 }  // namespace Aidge