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Commit 5a285f17 authored by Olivier BICHLER's avatar Olivier BICHLER Committed by Maxence Naud
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Fixed missing input for conv

parent fba9b16c
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......@@ -52,6 +52,7 @@ class test_OperatorImpl(unittest.TestCase):
self.assertTrue("cpu" in aidge_core.get_keys_ConvOp2D())
conv = aidge_core.Conv2D(2,2,[1,1], name="Conv0")
conv.get_operator().set_backend("cpu")
conv.get_operator().set_input(0, aidge_core.Tensor(np.arange(9).reshape(1,1,3,3)))
conv.get_operator().forward()
self.assertEqual(GLOBAL_CPT, 1)
......@@ -65,6 +66,7 @@ class test_OperatorImpl(unittest.TestCase):
conv = aidge_core.Conv2D(2,2,[1,1], name="Conv0")
model = aidge_core.sequential([conv])
model.set_backend("cpu")
conv.get_operator().set_input(0, aidge_core.Tensor(np.arange(9).reshape(1,1,3,3)))
conv.get_operator().forward()
self.assertEqual(GLOBAL_CPT, 1)
......
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