[5.2.0] 2026-03-13 - Testbench: add sequence that reads trace file from QEMU execution - Testbench: add direct mapped configuration and validate it in the CI - Add plugin for QEMU to generate memory access traces - Add cache invalidation signal in the memory response interface - Enable concurrent read and write if they target different banks - Optimize write byte enable logic for timing towards data SRAMs - Improve wake-up logic in the RTAB for requests waiting for a refill - Prevent invalidations to go into the uncached handler (on OpenPiton platform) - Correctly support direct mapped configuration of the cache