cv.avgu and cv.srl/sra/sll instructions out of sync

In https://github.com/openhwgroup/cv32e40p/commit/f2a1997cfd2379ca09ed89795ec4eb25cec9c1e7, a change of spec demands that the immediate argument of shift instructions no longer allow values greater than the number of bits in a register, while the testsuite still tests for values out of this range:

https://github.com/openhwgroup/corev-binutils-gdb/blob/8c3d27d122bdf3aab4205c0be7705ebe8db28bbf/gas/testsuite/gas/riscv/cv-simd-srl-sci-b-pass.d#L18

Similarly, https://github.com/openhwgroup/cv32e40p/commit/cdee092d6413ef0af53c63ac7eaf1d075be864ea changes cv.avgu to zero-extension(unsigned), while the testsuite still tests for negative values:

https://github.com/openhwgroup/corev-binutils-gdb/blob/8c3d27d122bdf3aab4205c0be7705ebe8db28bbf/gas/testsuite/gas/riscv/cv-simd-avgu-sci-b-pass.d#L17