Use of SystemVerilog Interface should be strongly discouraged

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Task Description

This repo hosts an example SystemVerilog Interface of the CV-X-IF in src/core_v_xif.sv. It should be made clear that this is a simulation only example and should not be used in any CORE-V RTL IP.

The CV32E40P coding style guidelines, which are essentially the lowRISC coding style guidelines, indicate that SystemVerilog Interfaces are problematic constructs and their use is discouraged.

Description of Done

core_v_xif.sv is a useful example, so it is proposed that we simply add the following to the comment header of that file:

// EXAMPLE ONLY
// The lowRISC coding style guidelines (https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md)
// indicate that SystemVerilog Interfaces are problematic constructs and their use in CORE-V RTL IP is strongly discouraged.