mcycle and minstret performance counter CSRs read always zero

According to the user manual (OVP_Model_Specific_Information_openhwgroup_riscv_CV32E40P.pdf) the performance counters mcycle and minstret are being implemented for the CV32E40P model while mtime should raise an illegal instruction exception.

This is actually true but somehow, rdcycle and rdinstret do always return zeros from the CSRs instead of actual values. Is this intentionally? The feature is working as expected with the (verilated) RTL of the CV32E40P as well as riscvOVPSimPlus.

This is maybe related to #1 but I am using standard RISC-V performance counters here and not am relying on semihosting functionality (gettimeofday())

Here is a minimal program (compiled with riscv32-unknown-elf-gcc -o test.elf test.c -march=rv32imc -mabi=ilp32) to reproduce the "Bug":

// test.c
#include <stdio.h>
#include <stdint.h>

static inline uint32_t rdcycle(void)
{
    uint32_t cycles;
    __asm__ volatile("rdcycle %0" : "=r"(cycles));
    return cycles;
}

int main() {
    uint32_t before = rdcycle();
    printf("Hello\n");
    uint32_t after = rdcycle();
    printf("Before: %u | After: %u\n", before, after);
    return 0;
}

Executing with ./riscv-ovpsim-corev-20230425/bin/Linux64/riscvOVPsimCOREV.exe --program test.elf --variant CV32E40P --processorname CVE4P leads to the following output:

...
Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'test.elf'
Info (OR_PH) Program Headers:
Info (OR_PH) Type           Offset     VirtAddr   PhysAddr   FileSiz    MemSiz     Flags Align
Info (OR_PD) PROC           0x0000fa35 0x00000000 0x00000000 0x00000039 0x00000000 R--   1
Info (OR_PD) LOAD           0x00000000 0x00010000 0x00010000 0x0000ea40 0x0000ea40 R-E   1000
Info (OR_PD) LOAD           0x0000f000 0x0001f000 0x0001f000 0x000009dc 0x00000a38 RW-   1000
Hello
Before: 0 | After: 0
Info
Info ---------------------------------------------------
Info CPU 'riscvOVPsim/cpu' STATISTICS
Info   Type                  : CVE4P (CV32E40P)
Info   Nominal MIPS          : 100
Info   Final program counter : 0x1b028
Info   Simulated instructions: 2,999
Info   Simulated MIPS        : run too short for meaningful result
Info ---------------------------------------------------
...

while ./riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe --program test.elf --variant RV32I --override riscvOVPsim/cpu/add_Extensions=MC is yielding to:

...
Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'test.elf'
Info (OR_PH) Program Headers:
Info (OR_PH) Type           Offset     VirtAddr   PhysAddr   FileSiz    MemSiz     Flags Align
Info (OR_PD) PROC           0x0000fa35 0x00000000 0x00000000 0x00000039 0x00000000 R--   1
Info (OR_PD) LOAD           0x00000000 0x00010000 0x00010000 0x0000ea40 0x0000ea40 R-E   1000
Info (OR_PD) LOAD           0x0000f000 0x0001f000 0x0001f000 0x000009dc 0x00000a38 RW-   1000
Hello
Before: 160 | After: 1123
Info
Info ---------------------------------------------------
Info CPU 'riscvOVPsim/cpu' STATISTICS
Info   Type                  : riscv (RV32I+CM)
Info   Nominal MIPS          : 100
Info   Final program counter : 0x1b028
Info   Simulated instructions: 3,390
Info   Simulated MIPS        : run too short for meaningful result
Info ---------------------------------------------------
...