Generating C.EBREAK without simulation could make RTL fails to execute test

Hi, there~

There is a description about building FORCE in FORCE-RISCV_User_Manual-v0.8.pdf, Chapter 2.1:

To build FORCE-RISCV, execute these commands.  It will take several minutes for the make commands to complete.
        cd force-riscv
        make
        make tests

After executing command "make tests", FORCE will generate some templates under tests/riscv/instructions. And I guess these templates are used to make sure that FORCE is able to generate all the instructions contained in the given configuration. And there is a special sub-directory “c_instructions/genonly” and I listed all its contained files below.

I tried to use T1-genonly_Group0-C-EBREAK-force.py to generate test without simulation(no-sim: True). The process of test generation is fine, but it failed when RTL design executes the test. After some debugging, I think C.EBREAK and SkipInstructionHandlerRISCV routine together could be the cause of failure.

   C.EBREAK //Instruction specified in template
   JAL           //EndOfTest

Executing C.BREAK brings core into trap mode. And the handler subroutine used to service this trap(err code is 3) in default comprehensive exception handlers is generated by SkipInstructionHandlerRISCV, which simply increase the return address by 4. So the PC returned from exception handler points to the middle of JAL.

Here are my questions:

1. What is the use of the above mentioned special sub-directory: genonly?
2. How to make RTL design successfully execute the above mentioned test?