[BUG] Misaligned load exceptions are reported with the wrong scause code.

Is there an existing CVA6 bug for this?

• I have searched the existing bug issues

Bug Description

Problem

• Executing hlv.d x14, 0(x10) with x10 = 0x8fffffdc (8-byte misaligned) should raise scause 0x4 (Load address misaligned).
• CVA6 instead reports scause 0x5, so the misaligned load trap is mis-encoded.

Reproduction

1. Run the following snippet on CVA6 and on Spike (reference core). Ensure the trap handler writes scause to a GPR (e.g., x17) for observation.

   li x10, 0x8fffffdc
   li x14, 0x0
   hlv.d x14, 0(x10)

2. After the trap, read back the recorded scause.
3. Spike reports 0x4, while CVA6 reports 0x5, demonstrating the incorrect encoding of the misaligned load exception.