[BUG] Retiming not applied to fpnew_fma during synthesis with DC

Hi, thank you for your great work on this project.

Recently, I encountered some timing issues when synthesizing the cv64a6_imafdc_sv39 core with the TSMC28 technology library (clk period = 0.8ns (1.25GHz)). Many modules from fpnew, such as fpnew_fma, show critical timing paths.

After checking existing issues, I learned that a common approach is to use retiming to balance the pipeline registers inside fpnew_fma. To apply retiming in Design Compiler, I used the following commands:

set_optimize_registers true -design [get_designs fpnew_fma*]
compile_ultra -no_autoungroup -gate_clock -retime

This should enable Adaptive Retiming and Pipelined-Logic Retiming in DC. However, during synthesis, I received the following warning:

Retiming fpnew_fma_1_00000003_3_902242 (ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma)
Warning: There are buffer or inverter cells in the
	clock tree. The clock tree has to be recreated after
	retiming. (RTDC-47)
  Preferred flip-flop is SDFOPTMCD12BWP40P140 with setup = 0.00

Warning: The following cells only drive
	asynchronous pins of sequential cells which have no
	timing constraint. Therefore retiming will not optimize
	delay through them:
	ex_stage_i/fpu_gen.fpu_i/fpu_gen.i_fpnew_bulk/gen_operation_groups[0].i_opgroup_block/gen_parallel_slices[1].active_format.i_fmt_slice/gen_num_lanes[0].active_lane.lane_instance.i_fma/*cell*571100 (INVD9BWP40P140)

 (RTDC-115)

There are still long critical paths in fpnew_fma, similar to that before using retiming.

Retiming base-clock clk_i, rising edge.
  Beginning minimum period retiming ...
  ... minimum period retiming done.
  Beginning minimum area retiming step 1 ...
  ... minimum area retiming step 1 done.
  Beginning minimum area retiming step 2 ...
  5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 
  ... minimum area retiming step 2 done.
  Beginning minimum area retiming step 3 ...
  10%   ... minimum area retiming step 1 done.
  Beginning minimum area retiming step 2 ...
  5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 60% 65% 70% 75% 80% 85% 90% 95% 100% 
  ... minimum area retiming step 2 done.
  Beginning minimum area retiming step 3 ...
  10% 20% 30% 40% 50% 60% 70% 80% ... 100% 
  ... minimum area retiming step 3 done.
  Beginning final register move ...
  ... final register move done.
  Lower bound estimate = 1.10
  Critical path length = 1.10
  Clock correction = 0.15 (clock-to-Q delay = 0.06, setup = 0.00, uncertainty = 0.09)

Could you please help me understand the cause of this issue? I’m not sure whether it’s related to my DC commands or something inside the fpnew_fma design itself.

Thanks again for your excellent work and support!