Extensions state save and restore

When using corev-openhw-gcc-centos7-20230331 toolchain with F extensions, all interrupt handlers blindly save and restore f registers without looking at Floating-Point state in MSTATUS register. Moreover it does not save/restore full state as FCSR is missing.

In RISC-V Privilege specification, Machine Status Register (mstatus) section shows some fields for extension states:

• FS for Floating-Point extension
• XS for user-mode or custom extensions
• VS for Vector extension and SD to summarize the dirtiness of all those 3 extensions.

When SD equals 1, this means that any of those 3 extensions has been used since they have been enabled or since the last context restore. So FS/XS/VS should be tested to understand which extension is "Dirty" and needs whole state save and restore when changing the execution context (interrupt route, context switch, etc,...).

When SD is 0, no state needs to be saved/restored and interrupt latency/context switch/... is improved because 33 registers write in memory (generally stack) are not done. Same for the state restore at the end of the interrupt routine/context switch/...

A full description of the FS/XS/VS state transitions is described in Table 3.4